1. Field of the Invention
This invention relates generally to methods of single and in-situ multiple integrated circuit processing steps, including chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), reactor cleaning and coating, and etching. The present invention also relates to a process for forming conformal, planar dielectric layers on integrated circuit wafers and to an in-situ multi-step process for forming conformal, planar dielectric layers that are suitable for interlevel dielectrics for multi-layer metalization interconnects and substrate contacts.
2. Description of the Prior Art
In recent years there continues to be a dramatic density increases in integrated circuit technology. The minimum feature size of lithography has been reduced to below one micrometer. In the fabrication of precision via and contact opening at these reduced dimensions, it is important to form insulating layers (inter metal dielectric (IMD), interlevel dielectric (ILD) layers) that have uniform wet etch rates so that uniform via and contact opening can be formed.
The inventor has found that high non-uniform Etch rates will form a non-uniform contact hole profile having a rough (zig-zag) 34 sidewall profile. See FIG. 1. These uneven sidewall profiles (zig zag shaped sidewalls) causes difficulties for the following sputter barrier (Ti/TiN layers) and tungsten. The Rc-Via will be high and the RC time delay will be lower. In general, the device signal transmitted speed is slowed.
FIG. 1 shows a metal layer 61 with an overlaying insulating layer 31. An opening 32 is formed in the insulating layer 31 using a wet etch that results in a rough sidewall 34.
The importance of overcoming the various deficiencies noted above is evidenced by the extensive technological development directed to the subject, as documented by the relevant patent and technical literature. The closest and apparently more relevant technical developments in the patent literature can be gleaned by considering U.S. Pat. No. 4,892,753 (Wang) shows a method of forming a PECVD silicon oxide layer using TEOS decomposition. U.S. Pat. No. 5,635,425 (Chen) shows another method for forming a PE-TEOS oxide layer.